1. Field of the Invention
This invention relates to electrically erasable programmable read-only memory (EEPROM) cells, and more particularly to a split gate transistor and common gate flash EEPROM cell.
2. Description of the Prior Art
With conventional split gate flash EEPROM cells a disadvantage exists in that, in addition to a standard 5 volt power supply used to read the cell, a secondary power supply of 12 volts is required to program the cell. In a conventional prior art cell, a floating gate is charged with electrons by channel hot-electron programming and the floating gate is discharged by Fowler-Nordheim tunneling of electrons from the floating gate to a drain region.
A typical prior art split gate flash EEPROM cell has been described in U.S. Pat. No. 4,783,766 issued Nov. 8, 1988, to G. Samachisa et al.
FIGS. 1 and 2 illustrate in simplified and greatly enlarged fashion first and second embodiments of a typical prior art split gate EEPROM cell such as that described in the above-referenced patent. FIG. 1 shows a cross section through a prior art EEPROM memory cell comprising various layers grown and/or deposited on P-type monocrystalline silicon substrate 1. Upon substrate 1 is grown a first gate oxide 4 having a thin dielectric portion 5. Thin dielectric portion 5 is typically formed using the well-known Kooi effect. A first polysilicon layer, which is lightly doped, is applied upon first gate oxide 4 and thin dielectric region 5, and thereafter masked and etched to define floating gate 6. Interpoly oxide 7 and second gate oxide 8 are then grown in a manner well known in the art. A second polysilicon layer is deposited over interpoly oxide 7 and second gate oxide 8, then doped, masked and etched to form control gate 9. Finally, substrate 1 is doped forming self-aligned source region 2 and drain region 3, having a small side diffusion located under one edge of control gate 9 and one edge of floating gate 6, respectively. Disposed below first gate oxide 4 and thin dielectric region 5 is first channel region 10. Below second gate oxide 8 and control gate 9 is second channel region 11 which abuts source region 2, but does not extend below floating gate 6.
FIG. 2 shows a second embodiment of the prior art EEPROM cell in which first gate oxide 4' is grown to a uniform thickness.
To erase the prior art EEPROM cells illustrated in FIGS. 1 and 2, a potential of approximately 17 to 20 volts is applied to the drain region 3, control gate 9 is grounded, and source region 2 is either grounded or allowed to float. Under these conditions electrons will tunnel from floating gate 6 through thin dielectric portion 5 into drain region 3 by virtue of the well-known Fowler-Nordheim tunneling effect. As a result, floating gate 6 achieves a positive potential. In erasing an EEPROM cell of FIG. 2, tunneling through first oxide 4' is obtained if the uniform thickness of first oxide 4' is limited to approximately 200 .ANG. or below.
In programming the prior art EEPROM cells of FIGS. 1 and 2, a potential of approximately 17 to 20 volts is applied to the control gate 9, drain region 3 is held at approximately 10 volts, and source region 2 is grounded. Under these conditions, electrons enter and are trapped by floating gate 6 by the channel hot electron injection phenomenon. As a result, floating gate 6 achieves a negative potential.
During a read operation, a potential of 5 volts is applied to control gate 9 and a potential of 2 volts is applied to drain region 3. If a net positive charge exists on floating gate 6 (i.e., an erase mode has been performed), then the channel region 10 will be open to current flow from drain region 3 to source region 2. Likewise, the 5-volt potential on control gate 9 will open channel region 11 to current flow from drain region 3 to source region 2. Therefore, if a net positive charge exists on floating gate 6, current will flow across channels 10 and 11 from drain region 3 to source region 2. If a net negative charge resides on floating gate 6, current from drain region 3 will be blocked from passing to source region 2 because channel region 10 will be nonconductive.
A disadvantage with the above-described prior art EEPROM cell is that in addition to a standard 5 volt power supply necessary to perform a read function, a second power supply of 12 volts or more is required to perform the programming function described above.